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A METHOD, APPARATUS, SYSTEM FOR EMBEDDED STREAM LANES IN A HIGH-PERFORMANCE INTERCONNECT
A METHOD, APPARATUS, SYSTEM FOR EMBEDDED STREAM LANES IN A HIGH-PERFORMANCE INTERCONNECT
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机译:高性能互连中嵌入式流道的方法,装置和系统
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摘要
In an example, a high-performance interconnect (HPI) is provisioned without a separate stream lane. To provide equivalent functionality, stream lane data are provided within data lines during idle periods. Because one stream lane may be provided per 20 data lanes, elimination of the stream lane saves approximately 5% of area. In a pre-data time, the 20 data lanes may be brought high from midrail to represent one species of data (for example, Intel® in-die interconnect (IDI)), and brought low to represent a second species of data (for example, Intel® on-chip system fabric (IOSF)). To represent additional species of data, such as link control packets (LCPs) for example, lanes can be divided into two or more groups, and a single bit can be encoded into each group. LCP can also be encoded into a post-data time, for example by ceasing flit traffic and manipulating a VALID lane from midrail to 0 or 1.
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