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SCALABLE NEUROMORIC CORE WITH SHARED SYNAPTIC MEMORY AND VARIABLE PRECISION SYNAPTIC MEMORY
SCALABLE NEUROMORIC CORE WITH SHARED SYNAPTIC MEMORY AND VARIABLE PRECISION SYNAPTIC MEMORY
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机译:具有共享突触存储器和可变精度突触存储器的可扩展神经元核心
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摘要
An electronic neuromorphic core processor circuit and related method include a processor, an electronic memory, and a dendrite circuit comprising an input circuit that receives an input spike message having an associated input identifier that identifies a distribution set of dendrite compartments. A synapse map table provides a mapping of the received identifier to a synapse configuration in the memory. A synapse configuration circuit comprises a routing list that is a set of synaptic connections related to the set of dendrite compartments, each being n-tuple information comprising a dendriteID and a weight stored in the memory. The synapse configuration circuit associates the identifier with the set of synaptic connections, a dendrite accumulator comprising a weighting array. It accumulates weight values within a dendritic compartment identified by the dendriteID and based on the n-tuple information associated with the set of synaptic connections associated with the identifier.
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