首页> 外国专利> TRELLIS DECODING WITH TRELLIS STATE REDUCTION BASED ON A-PRIORI KNOWLEDGE OF CONTROL CHANNEL BITS

TRELLIS DECODING WITH TRELLIS STATE REDUCTION BASED ON A-PRIORI KNOWLEDGE OF CONTROL CHANNEL BITS

机译:基于控制通道位先验知识的网格状态减少的网格译码

摘要

The disclosure relates to a decoding device, comprising: a receiver configured to provide a sequence of information bits comprising context redundancy information, wherein the sequence of information bits is encoded based on a predefined channel code; a trellis generation logic configured to generate a plurality of trellis states based on the sequence of information bits and the channel code; a trellis reduction logic configured to reduce the plurality of trellis states by at least one trellis state based on the context redundancy information; and a decoder configured to decode the sequence of information bits by using a metric based on the reduced number of trellis states.
机译:本公开涉及一种解码设备,包括:接收机,被配置为提供包括上下文冗余信息的信息比特的序列,其中,所述信息比特的序列基于预定义的信道码被编码;以及网格生成逻辑,被配置为基于信息比特序列和信道代码来生成多个网格状态;一种网格减少逻辑,其被配置为基于上下文冗余信息将多个网格状态减少至少一个网格状态;解码器,被配置为通过使用基于减少的网格状态数的度量来对信息比特序列进行解码。

著录项

  • 公开/公告号EP3273604A1

    专利类型

  • 公开/公告日2018-01-24

    原文格式PDF

  • 申请/专利权人 INTEL IP CORPORATION;

    申请/专利号EP20160179970

  • 发明设计人 ECKARDT FLORIAN;YU ZHIBIN;XU QING;

    申请日2016-07-18

  • 分类号H03M13/41;H04L1;H03M13/39;

  • 国家 EP

  • 入库时间 2022-08-21 13:15:29

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