Execution slice circuit for use within a processor core, processor core, and method for executing program instructions by processor core

摘要

An execution slice circuit for use within a processor core, a processor core, and a method for executing program instructions by the processor core. An execution slice circuit for a processor core has a plurality of parallel instruction execution slices to provide flexible and efficient use of internal resources. The execution slice circuit receives a master execution slice for receiving instructions of the first instruction stream, instructions of the second instruction stream, and instructions of the first instruction stream that require an execution width greater than the slice width. Slave execution slices for The execution slice circuit also includes control logic, which detects when the first instruction of the first instruction stream has the large execution width and is parallel across the master execution slice and the slave execution slice. The slave execution slice is controlled so as to reserve the first issue cycle for issuing the first instruction. [Selection] Figure 8