An image scaling processor includes: a coefficient computing circuit that calculates interpolation coefficients to be used in an image scaling process; a multiplier that multiplies input image data by the interpolation coefficients provided from the coefficient computing circuit such that the interpolation coefficients respectively correspond to input pixels constituting the input image data; an adder that iteratively adds pieces of multiplied data output from the multiplier and obtains a total sum of the pieces of multiplied data for a predetermined number of the input pixels; a selector that outputs a total sum of the multiplied data at a timing at which the total sum of the pieces of multiplied data is obtained for the predetermined number of the input pixels; and a shift circuit that shifts an output of the selector to adjust a bit count of the output image data to a bit count of the input image data.
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