Operation of a multi-slice processor implementing a mechanism to overcome a system hang

摘要

Operation of a multi-slice processor that includes execution slices and a dispatch network of the multi-slice processor implementing a hardware level mechanism to overcome a system hang. Such a multi-slice processor includes a plurality of execution slices and a dispatch network of the multi-slice processor implementing a hardware level mechanism to overcome a system hang. Operation of such a multi-slice processor includes, storing, in one or more logical units of a plurality of logical units of an age array, a logical value representing a relative age between instructions; propagating, in response to a current instruction being in a hang state, a hang signal to the plurality of logical units of the age array; in response to the hang signal, generating, from the plurality of logical units, a plurality of logical output values indicating a next instruction ready for execution; and issuing the next instruction for execution.