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Method and system for efficient block synchronization scheme on a scrambled cyclic code bit stream

机译:用于在加扰的循环码比特流上进行有效的块同步方案的方法和系统

摘要

An improved approach is provided to identifying the boundary of data encoded using additive cyclic codes. In some embodiment, the process includes determining a first calculated parity of a first bit stream window, and, second, one or more updates to the calculated parity of the bit stream window to determine the parity of the next bit stream window, where after each update to the calculated parity, the calculated parity is compared with the target parity, and matching the calculated parity to the target parity indicates a proper boundary of a bit stream window. In some embodiments, the process supports shortened cyclic codes. In some embodiments, the bit stream boundary can be identified prior to descrambling the bit stream inputs for a given bit stream window. In this way, the process can avoid unnecessarily descrambling of the bit stream windows that are not properly aligned to a bit stream boundary.
机译:提供了一种改进的方法来识别使用加性循环码编码的数据的边界。在一些实施例中,该过程包括确定第一比特流窗口的第一计算奇偶校验,以及第二,对比特流窗口的计算的奇偶校验进行一次或多次更新以确定下一比特流窗口的奇偶校验。更新到所计算的奇偶校验,将所计算的奇偶校验与目标奇偶校验进行比较,并且将所计算的奇偶校验与目标奇偶校验进行匹配指示比特流窗口的适当边界。在一些实施例中,该过程支持缩短的循环码。在一些实施例中,可以在解扰给定比特流窗口的比特流输入之前识别比特流边界。以这种方式,该过程可以避免不必要地解扰与比特流边界未正确对准的比特流窗口。

著录项

  • 公开/公告号US10020824B1

    专利类型

  • 公开/公告日2018-07-10

    原文格式PDF

  • 申请/专利权人 CADENCE DESIGN SYSTEMS INC.;

    申请/专利号US201615185828

  • 发明设计人 SARATH KUMAR JHA;

    申请日2016-06-17

  • 分类号H03M13/33;H03M13/09;H03M13;

  • 国家 US

  • 入库时间 2022-08-21 13:03:18

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