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PROCESSORS AND METHODS FOR MANAGING CACHE TIERING WITH GATHER-SCATTER VECTOR SEMANTICS
PROCESSORS AND METHODS FOR MANAGING CACHE TIERING WITH GATHER-SCATTER VECTOR SEMANTICS
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机译:用GATCHER-SCARTER向量语义学处理缓存分层的处理器和方法
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摘要
Processors and methods implementing a machine instruction to perform cache line demotion on multiple cache lines to enable efficient sharing of cache lines between processor cores. One general aspect includes a processor comprising: a plurality of hardware processor cores, where each of the hardware processor cores to include a first cache. The processor also includes a second cache, communicatively coupled to and shared by the plurality of hardware processor cores. The processor to support a first machine instruction, the first machine instruction to include a vector register operand identifying a vector register which contains a plurality of data elements each used to identify a cache line. An execution of the first machine instruction by one of the plurality of hardware processor cores to cause a plurality of identified cache lines to be demoted, such that the demoted cache lines are moved from the first cache to the second cache.
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