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Method to Perform Full Accuracy Hierarchical Block Level Timing Analysis with Parameterized Chip Level Contexts
Method to Perform Full Accuracy Hierarchical Block Level Timing Analysis with Parameterized Chip Level Contexts
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机译:参数化芯片级上下文执行全精度分层块级时序分析的方法
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摘要
A method and apparatus for on chip variation path-based pessimism reduction and improving analysis of a hierarchical integrated circuit design in an electrical circuit. The circuit has one or more block circuit levels and a top circuit level. The method in one embodiment comprises characterizing the top circuit level to produce a context function, the context function used by the block circuit level for evaluation.
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