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Byte and nibble sort instructions that produce sorted destination register and destination index mapping
Byte and nibble sort instructions that produce sorted destination register and destination index mapping
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机译:字节和半字节排序指令,产生已排序的目标寄存器和目标索引映射
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摘要
A processor comprises a first register to store a plurality of data items at a plurality of positions within the first register, a second register, and an execution unit, operatively coupled to the first register and the second register, the execution unit comprising a logic circuit implementing a sort instruction for sorting the plurality of data items stored in the first register in an order of data item values, and storing, in the second register, a plurality of indices, wherein each index identifies a position associated with a data item stored in the first register prior to the sorting.
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