Digital signal processor and method to address a memory in a digital signal processor

摘要

A digital signal processor (200) comprising at least one functional unit, which may be a vector execution unit (203, 205), or an accelerator, and at least a first memory unit (230, 231) arranged for provide data to be operated by the functional unit, a third unit (250) and a chip network (244) that connects the functional unit, the first memory unit and the third unit, said digital signal processor being characterized in that the third unit (250) is arranged to provide addressing data in the form of an address vector to be used to address the first memory unit (230, 231), said third unit being connectable to the first memory unit (230, 231 ) such that the addressing data can be used to control the reading of and / or writing to the first memory unit (230, 231) and because the processor further comprises an address interface unit d e memory (256) disposed between the first memory unit and the chip network to compensate for the latency between the first memory unit and the third unit serving as an intermediate storage of the addressing data recovered from the third unit, where the memory address interface unit is arranged to, when the first memory unit is configured to receive the addressing data of the third unit, start reading the addressing data of the third unit before the first memory unit Request the addressing data.