HARDWARE AND SOFTWARE SOLUTIONS TO DIVERGENT BRANCHES IN A PARALLEL PIPELINE

摘要

A system and method for efficient processing of instructions in a hardware parallel execution lane within a processor is disclosed. In response to a given branch point in the identified loop, the compiler arranges the instructions in the loop to be identified into a VLIW (very large instruction world). At least one VLIW refers to instructions intermixed from different basic blocks between a given branch point and a corresponding concentration point. The compiler, when executed, generates code that, at runtime, assigns instructions in a given VLIW to a plurality of parallel execution lanes in a target processor. The target processor includes a single instruction multiple word (SIMD) microstructure. The assignment for a given lane is based on the branch direction found at runtime for a given lane at a given branch point. The target processor includes a vector register for storing an indication indicating a given instruction in the drawn VLIW to be executed by the associated lane.