-- APPARATUS AND METHOD FOR TOPOLOGY DESIGN ON ASYNCHRONOUS NETWORK-ON-CHIP

摘要

The present invention relates to an asynchronous network-on-chip designing apparatus which includes a memory storing program for designing the topology and a processor for executing the program stored in the memory. The processor derives a delay time model corresponding to a network-on-chip based on information corresponding to the network-on-chip in accordance with the execution of the program. The processor also selects topology with the minimum delay time corresponding to the network-on-chip based on the delay time model. The network-on-chip includes multiple routers. Each of the routers is connected to one or more other routers. The information corresponding to the network-on-chip includes the information on the paths between the individual routers and the number of routers included in the network-on-chip, and the topology includes links between the individual routers.