SYSTEM AND METHOD FOR PROVIDING AREA EFFICIENT AND DESIGN RULE CHECK FRIENDLY POWER SEQUENCER FOR DIGITAL CIRCUITS

摘要

According to the present invention, an apparatus provides an area efficient and design rule check friendly power sequencer for digital circuits comprises a power header and a logic circuit. The power header may include a gate terminal, a first channel terminal, a second channel terminal, and a bulk terminal coupled to a first power supply voltage signal, and dynamically connect or disconnect the first power supply voltage signal to a logic circuit. The logic circuit may include a bulk terminal connected to a second power supply voltage signal, and a power supply terminal dynamically connected or disconnected to the first power supply voltage signal according to determination of the power header. A power sequencing signal which can be included in the apparatus may control the power header. When the power sequencing signal is activated, the power header couples the first power supply voltage signal to the logic circuit after the second power supply voltage signal rises to a high level.;COPYRIGHT KIPO 2018