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IMPEDANCE MAGNITUDE MEASUREMENT CIRCUIT USING TIME-OFFSET-BASED SELF-SAMPLING SCHEMES AND IMPEDANCE MAGNITUDE AND PHASE MEASUREMENT DEVICE USING THE SAME
IMPEDANCE MAGNITUDE MEASUREMENT CIRCUIT USING TIME-OFFSET-BASED SELF-SAMPLING SCHEMES AND IMPEDANCE MAGNITUDE AND PHASE MEASUREMENT DEVICE USING THE SAME
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机译:使用基于时间偏移的自采样方案的阻抗幅度测量电路以及使用相同时间的阻抗幅度和相位测量设备
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摘要
An apparatus for measuring impedance magnitude and phase using time offset based self-sampling techniques is disclosed. From the reference signal and the cell signal appearing respectively in the reference resistance and the cell to be measured, two clock signals are obtained by using two comparators, and the phase of the impedance is measured by XOR or XNOR operation of the clock signals. When a signal less than a predetermined frequency is applied, sampling of the reference signal and the material signal is performed using the two clock signals. When a signal over a predetermined frequency is applied, sampling is performed through the clock signals generated using the DC integrators, the comparators, and the logic circuits to measure the magnitude of the impedance. For all desired frequency ranges, the magnitude of the impedance may be measured by sampling through clock signals generated through DC integrators, comparators and logic circuits. The present invention utilizes self-generated clock signals without a fast external clock signal and achieves low power operation and miniaturization of the device by minimizing the capacitance used.
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