Zero padded fast Fourier transform apparatus and method

摘要

The present invention relates to a zero padded fast Fourier transform (FFT) apparatus and a method thereof, capable of reducing complexity by reducing a circuit area of a delay portion in a pipelined FFT. The number of delay elements is remarkably reduced by utilizing the characteristic of zero padded input data and the feature that the operation of a first twiddle factor of a radix-2^ SDF or a radix-2^3 SDF pipeline structure is a simple multiplication by -j, thereby reducing complexity and power consumption. In particular, by using a shift register, which has the same length as a shift register of a second stage, in a first stage, the shift register of the first stage can be reduced by 50%. Therefore, the length of the entire shift register can be reduced by 25% so that the productivity and the yield rate can be increased.