Branch target variant of branch-with-link instruction

摘要

An apparatus comprises an instruction decoder to decode instructions and processing circuitry to perform data processing in response to those instructions. In response to a branch instruction (BI), the instruction decoder is configured to control the processing circuitry to trigger a non-sequential change of program flow to an instruction at a target address. When the non-sequential change of program flow is triggered in response to a branch-with-link (BLR) instruction, the instruction decoder is configured to control the processing circuitry to set a return address for a subsequent return of program flow. When the non-sequential change of program flow is triggered in response to at least one target-checking type of BI (TBI), the instruction decoder is configured to control the processing circuitry to trigger an error handling response when the instruction at the target address is an instruction other than at least one permitted type of branch target instruction (BTI). For at least a subset of said at least one TBI, said at least one BTI includes a branch target variant of the branch-with-link instruction (BLRTI). In response to the BLRTI, the processing circuitry may be configured to set the return address to an address of the BLRTI.