首页> 外国专利> A low-jitter end-to-end latency control scheme for isochronous communications based on transmitter timestamp information

A low-jitter end-to-end latency control scheme for isochronous communications based on transmitter timestamp information

机译:基于发射机时间戳信息的同步通信的低抖动端到端延迟控制方案

摘要

A latency control mechanism for a communication system provides a known constant end-to-end delay between an audio source and one or more end node destinations, even in the case where different paths are used to reach the end nodes. A very low jitter time on the end-to-end latency is obtained, and the latency is controllable within a given range in dependence on the constraints imposed by the implementation. A block RX DPLL and latency control unit adjusts the reading moment and position from the RX buffer so that a delay between the time stamp taken at the source side by the transmitter time stamp unit, and the time stamp taken at the receiver side by receiver time stamp unit is constant and equal to a given value.
机译:用于通信系统的等待时间控制机制即使在使用不同路径到达端节点的情况下,也可以在音频源与一个或多个端节点目的地之间提供已知的恒定的端到端延迟。在端到端等待时间上获得了非常低的抖动时间,并且根据实现所施加的约束,可以将等待时间控制在给定范围内。块RX DPLL和等待时间控制单元调整从RX缓冲区读取的时刻和位置,以使发送器时间戳单元在源侧获取的时间戳与接收器时间在接收器侧获取的时间戳之间具有延迟印记单位恒定且等于给定值。

著录项

  • 公开/公告号EP2341744B1

    专利类型

  • 公开/公告日2019-02-20

    原文格式PDF

  • 申请/专利权人 NXP B.V.;

    申请/专利号EP20100196165

  • 申请日2010-12-21

  • 分类号H04W56/00;H04J3/06;

  • 国家 EP

  • 入库时间 2022-08-21 12:30:21

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