首页> 外国专利> A MARCHING MEMORY, A BIDIRECTIONAL MARCHING MEMORY, A COMPLEX MARCHING MEMORY AND A COMPUTER SYSTEM, WITHOUT THE MEMORY BOTTLENECK

A MARCHING MEMORY, A BIDIRECTIONAL MARCHING MEMORY, A COMPLEX MARCHING MEMORY AND A COMPUTER SYSTEM, WITHOUT THE MEMORY BOTTLENECK

机译:没有内存螺栓的行进式存储器,双向行进式存储器,复杂的行进式存储器和计算机系统

摘要

A marching memory includes an array of memory units (Ui, U2, U3,........., Un-1, Un), each of the memory units having a sequence of bit-level cells (M11, M21, M31, ........, Mm-1,1, Mm1) so as to store information of byte size or word size. Each of the bit-level cells encompasses a transfer-transistor (Q111) having a first main-electrode connected to a clock signal supply line (CLOCK) through a first delay element (D111) and a control-electrode connected to an output terminal of a first neighboring bit-level cell disposed at input side of the array, through a second delay element (D112), a reset-transistor (Q112) having a control-electrode connected to the clock signal supply line, and a capacitor (C11) connected in parallel with the reset-transistor.
机译:行进存储器包括一组存储单元(Ui,U 2 ,U 3 ,.........,U n-1 < / Sub>,U n ),每个存储单元都有一系列的位元单元(M 11 ,M 21 ,M 31 ,........,M m-1,1 ,M m1 ),以便存储字节大小的信息或字号。每个位级单元都包含一个传输晶体管(Q 111 ),该晶体管具有通过第一延迟元件(D 111)连接到时钟信号供应线(CLOCK)的第一主电极)和控制电极,通过第二延迟元件(D 112 )连接到位于阵列输入侧的第一相邻位元单元的输出端子,该复位电极复位-晶体管(Q 112 )具有与时钟信号供应线连接的控制电极,以及与复位晶体管并联连接的电容器(C 11 )。

著录项

  • 公开/公告号EP3477645A1

    专利类型

  • 公开/公告日2019-05-01

    原文格式PDF

  • 申请/专利权人 NAKAMURA TADAO;FLYNN MICHAEL J.;

    申请/专利号EP20180000889

  • 发明设计人 NAKAMURA TADAO;FLYNN MICHAEL J.;

    申请日2013-02-13

  • 分类号G11C19/18;G11C19/28;

  • 国家 EP

  • 入库时间 2022-08-21 12:26:30

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