A marching memory includes an array of memory units (Ui, U2, U3,........., Un-1, Un), each of the memory units having a sequence of bit-level cells (M11, M21, M31, ........, Mm-1,1, Mm1) so as to store information of byte size or word size. Each of the bit-level cells encompasses a transfer-transistor (Q111) having a first main-electrode connected to a clock signal supply line (CLOCK) through a first delay element (D111) and a control-electrode connected to an output terminal of a first neighboring bit-level cell disposed at input side of the array, through a second delay element (D112), a reset-transistor (Q112) having a control-electrode connected to the clock signal supply line, and a capacitor (C11) connected in parallel with the reset-transistor.
展开▼