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NEW SSD BASIC STRUCTURE FOR FPGA-BASED ACCELERATION

机译:用于基于FPGA的加速的新SSD基本结构

摘要

To provide an SSD system which can accelerate load of data from an SSD to a memory.SOLUTION: The present invention includes: a CPU for executing an application; a memory for storing data used by an application being executed on the CPU; an upstream I/F for communicating with the CPU; a downstream I/F for communicating with a storage device; and an acceleration module realized by hardware, the acceleration module having an acceleration platform manager, APFM for executing an acceleration command. The storage device includes: an end point for the storage device for communicating with the acceleration module; a controller for managing the operation of the storage device; a store for storing application data for the application; and the APFM for the storage device helping the APFM of the acceleration module when the acceleration command is executed. The CPU, the acceleration module, and the storage device communicate via a PCIe bus. The acceleration module executes the acceleration command without loading the application data on the storage device into the memory.SELECTED DRAWING: Figure 1
机译:提供一种可以加速从SSD到存储器的数据加载的SSD系统。存储器,用于存储在CPU上执行的应用所使用的数据;与CPU通信的上游I / F;用于与存储设备通信的下游I / F;加速模块由硬件实现,加速模块具有用于执行加速命令的加速平台管理器APFM。该存储设备包括:用于与加速模块通信的存储设备的端点;用于管理存储设备的操作的控制器;用于存储应用程序的应用程序数据的商店;当执行加速命令时,用于存储设备的APFM帮助加速模块的APFM。 CPU,加速模块和存储设备通过PCIe总线进行通信。加速模块执行加速命令时不会将存储设备上的应用程序数据加载到内存中。

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