HIGH-LEVEL SYNTHESIS METHOD, HIGH-LEVEL SYNTHESIS PROGRAM, AND HIGH-LEVEL SYNTHESIS APPARATUS

摘要

To provide a high-level synthesis apparatus, a high-level synthesis method and a high-level synthesis program capable of reducing the number of clocks consumed by a logic circuit and increasing the speed by combining timings into the same timing on a logic circuit clock for memory reading occurred at the time of array reading.SOLUTION: When an operation description including a plurality of descriptions read in different memories is input, the operation description is changed so that the descriptions read in different memories are read at the same timing on a logic circuit clock before conditional branching, the operation description so changed is output, and thereby clocks consumed by the logic circuit can be reduced in number and can be increased in speed.SELECTED DRAWING: Figure 10