Compiler techniques for mapping program code to high-performance, power-efficient, programmable image processing hardware platforms

摘要

One method is described. The method comprises compiling targeted program code of an image processor having a programmable stencil processor consisting of respective two dimensional execution lanes and shift register circuitry. The program code implements a directed acyclic graph and consists of multiple kernels executed on each of the stencil processors, and compiling has a different number of kernels in the program code than the stencil processors in the image processor Recognize that at least one of the kernels is more computationally intensive than another of the kernels, and the program code has a resource requirement that exceeds the memory capacity of the image processor Recognize, including any. Compiling may further, in response to any of the above recognizing, horizontal fusion of kernels, vertical fusion of kernels, splitting of kernels into one, multiple kernels, multiple spatial divisions of kernels Including performing either a spatial partitioning into a kernel, or a partitioning of a directed acyclic graph into smaller graphs.