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Digital phase locked loop, control method thereof, and ultra-low power transceiver using the same
Digital phase locked loop, control method thereof, and ultra-low power transceiver using the same
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机译:数字锁相环,其控制方法以及使用其的超低功耗收发器
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摘要
A phase-locked loop (PLL) includes a counter configured to measure voltage-controlled oscillator (VCO) information of an oscillator during a mask time, and a frequency tuner configured to tune a frequency of the oscillator to a target frequency, based on a comparison result obtained by comparing the VCO information to target frequency information.
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