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System, method, and computer program product for capture and reuse in a debug workspace

机译:用于在调试工作空间中捕获和重用的系统,方法和计算机程序产品

摘要

The present disclosure relates to a method for reusing a debugging workspace in an electronic design environment. Embodiments may include performing, using a processor, a verification of an electronic design and identifying at least one triggered property associated with the electronic design. Embodiments may further include identifying at least one fan-in signal associated with the at least one triggered property of the electronic design. Embodiments may also include determining a start point debug location based upon, at least in part, the at least one fan-in signal, wherein the start point debug location includes at least one of signal information, cycle information, and event time information. Embodiments may further include generating a debug workspace, wherein generating includes adding at least one additional debug location and storing a cycle of the additional debug location as a relative cycle that is relative to another debug location associated with the debug workspace.
机译:本公开涉及一种用于在电子设计环境中重用调试工作空间的方法。实施例可以包括使用处理器执行电子设计的验证以及识别与电子设计相关联的至少一个触发特性。实施例可以进一步包括识别与电子设计的至少一个触发特性相关联的至少一个扇入信号。实施例还可包括至少部分地基于至少一个扇入信号来确定起点调试位置,其中,起点调试位置包括信号信息,周期信息和事件时间信息中的至少一个。实施例可以进一步包括生成调试工作空间,其中生成包括添加至少一个附加调试位置并将该附加调试位置的周期存储为相对于与该调试工作空间相关联的另一调试位置的相对周期。

著录项

  • 公开/公告号US10331547B1

    专利类型

  • 公开/公告日2019-06-25

    原文格式PDF

  • 申请/专利权人 CADENCE DESIGN SYSTEMS INC.;

    申请/专利号US201715602415

  • 发明设计人 CHIEN-LIANG LIN;CHUNG-WAH NORRIS IP;

    申请日2017-05-23

  • 分类号G06F11;G06F11/36;G06F17/50;

  • 国家 US

  • 入库时间 2022-08-21 12:15:34

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