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System and method for generating reduced standard delay format files for gate level simulation
System and method for generating reduced standard delay format files for gate level simulation
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机译:用于生成简化的标准延迟格式文件以进行门级仿真的系统和方法
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摘要
A system and method for generating standard delay format (SDF) files is disclosed. For each timing closed hierarchical instance, timing arcs on internal register to register paths may be marked as zero delay arcs. If the zero delay causes a hold violation, an adjustment may be computed to fix the violation. If the adjustment does not cause a setup violation, the adjustment may be applied to the end point register.
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