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Low power data transfer for memory subsystem using data pattern checker to determine when to suppress transfers based on specific patterns
Low power data transfer for memory subsystem using data pattern checker to determine when to suppress transfers based on specific patterns
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机译:用于内存子系统的低功耗数据传输,使用数据模式检查器确定何时基于特定模式抑制传输
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摘要
Systems and method are directed to reducing power consumption of data transfer between a processor and a memory. A data to be transferred on a data bus between the processor and the memory is checked for a first data pattern, and if the first data pattern is present, transfer of the first data pattern is suppressed on the data bus. Instead, a first address corresponding to the first data pattern is transferred on a second bus between the processor and the memory. The first address is smaller than the first data pattern. The processor comprises a processor-side first-in-first-out (FIFO) and the memory comprises a memory-side FIFO, wherein the first data pattern is present at the first address in the processor-side FIFO and at the first address in the memory-side FIFO.
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