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Method and apparatus for differential power analysis (DPA) resilience security in cryptography processors
Method and apparatus for differential power analysis (DPA) resilience security in cryptography processors
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机译:用于密码处理器中的差分功率分析(DPA)弹性安全性的方法和装置
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摘要
In certain aspects, a circuit includes a dynamic differential logic gate having first and second outputs, and a first static differential logic gate having first and second outputs, and first and second inputs coupled to the first and second outputs, respectively, of the dynamic differential logic gate. The dynamic differential logic gate is configured to receive a clock signal and to preset both the first and second outputs of the dynamic differential logic gate to a first preset value during a first phase of the clock signal. The first static differential logic gate is configured to preset both the first and second outputs of the first static differential logic gate to a second preset value when the first preset value is input to both the first and second inputs of the first static differential logic gate.
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