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Finite impulse response analog receive filter with amplifier-based delay chain

机译:带有基于放大器的延迟链的有限脉冲响应模拟接收滤波器

摘要

High-data rate channel interface modules and equalization methods employing a finite impulse response (FIR) analog receive filter. Embodiments include an illustrative channel interface module having multiple amplifier-based delay units arranged in a sequential chain to convert an analog input signal into a set of increasingly-delayed analog signals that are weighted and combined together with the analog input signal to form an equalized signal; and a symbol decision element operating on the equalized signal to obtain a sequence of symbol decisions. An interface that extracts received data from the sequence of symbol decisions. The delay units may employ one or more delay cells each having a common-source amplifier stage followed by a source follower output stage, the two stages providing approximately equal portions of the propagation delay. An enhanced gate-to-drain capacitance in the common-source amplifier may increase propagation delay while reducing bandwidth limitations.
机译:采用有限冲激响应(FIR)模拟接收滤波器的高数据速率通道接口模块和均衡方法。实施例包括说明性的信道接口模块,该信道接口模块具有布置在顺序链中的多个基于放大器的延迟单元,以将模拟输入信号转换成一组逐渐延迟的模拟信号,该模拟信号被加权并与模拟输入信号组合在一起以形成均衡信号。 ;符号判定元件,对均衡后的信号进行运算,以获得符号判定序列。一个从符号决策序列中提取接收到的数据的接口。延迟单元可以采用一个或多个延迟单元,每个延迟单元具有一个公共源极放大器级,其后跟随一个源极跟随器输出级,这两个级提供传播延迟的大约相等的部分。共源极放大器中增强的栅漏电容可以增加传输延迟,同时减少带宽限制。

著录项

  • 公开/公告号US10313165B2

    专利类型

  • 公开/公告日2019-06-04

    原文格式PDF

  • 申请/专利权人 CREDO TECHNOLOGY GROUP LIMITED;

    申请/专利号US201715453774

  • 发明设计人 LAWRENCE CHI FUNG CHENG;HAIHUI LUO;

    申请日2017-03-08

  • 分类号H03F3/21;H03F3/193;H04L25/03;H04L27/01;H03F3/45;H03G5/28;H03H11/26;H03H15/02;

  • 国家 US

  • 入库时间 2022-08-21 12:11:55

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