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Method to efficiently trigger concurrency bugs based on expected frequencies of execution interleavings

机译:基于执行交织的预期频率有效触发并发错误的方法

摘要

A method includes determining a set of shared memory access instructions and execution frequencies and selecting one or more groups of instructions that access a same memory location. The method also includes finding pairs of instructions from each group, for which another access to the same memory location may occur between execution of the instructions in the pair, and estimating a probability that a data race may occur using a time gap between the instructions and the execution frequencies, and generating a list of instruction tuples that include the pair of instructions. The method includes calculating a score for each instruction in the tuples, the score representing a likelihood of triggering a data race by injecting a delay before an instruction. The method includes selecting instructions having a score indicating a lower than a threshold probability that the instruction will comprise a last access of a data race.
机译:一种方法包括确定一组共享存储器访问指令和执行频率,以及选择访问同一存储器位置的一组或多组指令。该方法还包括从每个组中查找指令对,在该对指令中,在执行该对指令之间可能会再次访问同一存储位置;并使用这些指令之间的时间间隔来估计发生数据争用的可能性。执行频率,并生成包含该对指令的指令元组列表。该方法包括为元组中的每个指令计算分数,该分数表示通过在指令之前注入延迟来触发数据竞争的可能性。该方法包括选择具有分数的指令,该分数指示低于该指令将包括数据竞争的最后访问的阈值概率。

著录项

  • 公开/公告号US10191833B2

    专利类型

  • 公开/公告日2019-01-29

    原文格式PDF

  • 申请/专利权人 VMWARE INC.;

    申请/专利号US201514961504

  • 发明设计人 HAO CHEN;BO CHEN;

    申请日2015-12-07

  • 分类号G06F11/36;

  • 国家 US

  • 入库时间 2022-08-21 12:10:15

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