SQUARE ROOT DIGIT RECURRENCE

摘要

A data processing apparatus is provided, for performing a digit-recurrence square root operation on an input value. Receiver circuitry receives a remainder value of a previous iteration of the digit-recurrence square root operation. Comparison circuitry compares most significant bits of the remainder value of the previous iteration with a number of selection constants, in order to output a next digit of a result of the digit-recurrence square root operation. The comparison circuitry compares at most 3 fractional bits of the remainder value of the previous iteration with the plurality of selection constants.