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Method and apparatus for finding logic equivalence between register transfer level and post synthesis nets
Method and apparatus for finding logic equivalence between register transfer level and post synthesis nets
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机译:查找寄存器传输级和后合成网之间的逻辑等效性的方法和装置
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摘要
A method, computer program, and apparatus are described for finding the logical equivalence between register transfer level (RTL) wires and post synthesis nets in a netlist. In some example embodiments, the method includes minimizing nets in a netlist and matching each RTL wire to a netlist net. In some example embodiments, the method also includes determining if an RTL wire is logically equivalent to a netlist net. In some example embodiments, the method also includes determining a new candidate for a net if the RTL wire and associated netlist net are not logically equivalent.
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