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Configurable on-chip interconnection system and method and apparatus for implementing same, and storage medium

机译：可配置的片上互连系统及其实现方法和装置以及存储介质

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摘要

A method for implementing a configurable on-chip interconnection system. The method comprises: in an interconnection system, master devices set bit widths of bus identifiers of the master devices, wherein the bit widths of the bus identifiers of the master devices are the same (301); and in a memory access process, the mater devices interact, by means of interconnection matrices only, with slave devices according to the bus identifiers (302). Also provided are a system and apparatus for implementing the method, and a storage medium.

机译：一种用于实现可配置的片上互连系统的方法。该方法包括：在互连系统中，主控设备设置主控设备的总线标识的位宽，其中，主控设备的总线标识的位宽相同（ 301 ）;并且在存储器访问过程中，主设备仅通过互连矩阵与从设备根据总线标识符（ 302 ）进行交互。还提供了用于实现该方法的系统和装置以及存储介质。 展开▼

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公开/公告号US10198374B2

专利类型

公开/公告日2019-02-05

原文格式PDF

申请/专利权人 SANECHIPS TECHNOLOGY CO. LTD.;
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申请/专利号US201515527862

发明设计人 JIANPING JIANG;
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申请日2015-04-15

分类号G06F13;G06F13/16;G06F13/38;G06F13/40;G06F13/42;G06F13/364;

国家 US

入库时间 2022-08-21 12:08:48

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