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METHODS AND ARRANGEMENTS TO MANAGE MEMORY IN CASCADED NEURAL NETWORKS

机译:级联神经网络中管理内存的方法和安排

摘要

Logic may reduce the size of runtime memory for deep neural network inference computations. Logic may determine, for two or more stages of a neural network, a count of shared block allocations, or shared memory block allocations, that concurrently exist during execution of the two or more stages. Logic may compare counts of the shared block allocations to determine a maximum count of the counts. Logic may reduce inference computation time for deep neural network inference computations. Logic may determine a size for each of the shared block allocations of the count of shared memory block allocations, to accommodate data to store in a shared memory during execution of the two or more stages of the cascaded neural network. Logic may determine a batch size per stage of the two or more stages of a cascaded neural network based on a lack interdependencies between input data.
机译:逻辑可以减少用于深度神经网络推理计算的运行时内存的大小。对于神经网络的两个或更多个阶段,逻辑可以确定在两个或更多个阶段的执行期间同时存在的共享块分配或共享存储块分配的计数。逻辑可以比较共享块分配的计数以确定计数的最大计数。逻辑可以减少用于深度神经网络推理计算的推理计算时间。逻辑可以确定共享存储器块分配的计数中的每个共享块分配的大小,以容纳在级联神经网络的两个或更多个阶段的执行期间要存储在共享存储器中的数据。逻辑可基于输入数据之间缺乏相互依赖性来确定级联神经网络的两个或更多个阶段中每个阶段的批处理大小。

著录项

  • 公开/公告号US2019042925A1

    专利类型

  • 公开/公告日2019-02-07

    原文格式PDF

  • 申请/专利权人 INTEL CORPORATION;

    申请/专利号US201815954767

  • 申请日2018-04-17

  • 分类号G06N3/063;G06N3/04;G06F12/02;

  • 国家 US

  • 入库时间 2022-08-21 12:04:08

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