TECHNOLOGIES FOR RAPID CONFIGURATION OF FIELD-PROGRAMMABLE GATE ARRAYS

摘要

Technologies for rapid reconfiguration of a field programmable gate array (FPGA) are disclosed. A compute device, which may include the (FPGA), may select a new bitstream to load into the (FPGA). The compute device may compare the new bitstream against a current bitstream corresponding to the current configuration of the (FPGA) and determine the differences between the new bitstream and the current bitstream. The compute device may then encode the differences between the new bitstream and the current bitstream into a codestream and load the codestream into the (FPGA). The (FPGA) may then decode the codestream and update the memory locations of the FPGA such as settings of logic blocks and interconnects that are not the same between the new bitstream and the current bitstream.