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NOVEL SUBSURFACE BUOY DATA ACQUISITION SYSTEM

机译:新型地下浮标数据采集系统

摘要

A novel subsurface buoy data acquisition system, comprising: a battery compartment (1), a master control processor (2), a GPS receiver (3), a gigabit Ethernet interface module (4), and multiple data acquisition boards. The GPS receiver (3) is connected to the master control processor (2); the master control processor (2) is connected to an upper computer (6) by means of the gigabit Ethernet interface module (4); the data acquisition board comprises a hydrophone sensor (51), a front-end drive circuit (52), an AD conversion circuit (53), a clock module (54), a DA conversion circuit (55), an FPGA (56), an ARM processor (57), and a storage module (58); the hydrophone sensor (51) is connected to the AD conversion circuit (53) by means of the front-end drive circuit (52); the AD conversion circuit (53) is connected to the FPGA (56); the FPGA (56) is connected to the ARM processor (57); the storage module (58) is connected to the ARM processor (57); the DA conversion circuit (55) is connected to the FPGA (56) and the clock module (54); the clock module (54) is connected to the FPGA (56); and the ARM processor (57) is connected to the master control processor (2). The acquisition performance of a subsurface buoy data acquisition system is improved, and synchronous acquisition and control of the entire system are implemented.
机译:一种新颖的水下浮标数据采集系统,包括:电池仓(1),主控处理器(2),GPS接收器(3),千兆以太网接口模块(4)和多个数据采集板。 GPS接收器(3)连接到主控处理器(2);主控处理器(2)通过千兆以太网接口模块(4)连接到上位机(6);数据采集​​板包括水听器传感器(51),前端驱动电路(52),AD转换电路(53),时钟模块(54),DA转换电路(55),FPGA(56) ,ARM处理器(57)和存储模块(58);水听器传感器(51)通过前端驱动电路(52)与AD转换电路(53)连接。 AD转换电路(53)连接到FPGA(56)。 FPGA(56)连接到ARM处理器(57);存储模块(58)与ARM处理器(57)连接; DA转换电路(55)连接到FPGA(56)和时钟模块(54)。时钟模块(54)连接到FPGA(56); ARM处理器(57)连接到主控制处理器(2)。提高了水下浮标数据采集系统的采集性能,实现了整个系统的同步采集和控制。

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