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MULTIPHASE CLOCK DATA RECOVERY WITH ADAPTIVE TRACKING FOR A MULTI-WIRE, MULTI-PHASE INTERFACE
MULTIPHASE CLOCK DATA RECOVERY WITH ADAPTIVE TRACKING FOR A MULTI-WIRE, MULTI-PHASE INTERFACE
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机译:具有多线,多相接口的自适应跟踪的多相时钟数据恢复
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摘要
Data communication apparatus and methods for a multi-wire interface are disclosed. A half rate clock and data recovery (CDR) circuit derives a clock signal including pulses corresponding to symbols transmitted on a 3-wire interface, where the symbols are transmitted at a particular frequency with each of the symbols occurring over a unit interval (UI) time period. The first clock signal is input to a flip-flop logic included in a delay loop, and serves to trigger the first flip-flop logic. A second clock signal is generated using a programmable generator in the delay loop and has a frequency of a half UI and is fed back to a data input of the flip-flop. The output of the flip-flop is used as a recovered clock signal for the CDR at a half rate frequency. This design provides ease of timing control, a delay line without extra nonlinear-effects, and less hardware overhead.
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