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3D NAND 3D SEMICIRCULAR VERTICAL NAND STRING WITH SELF ALIGNED FLOATING GATE OR CHARGE TRAP CELL MEMORY CELLS AND METHODS OF FABRICATING AND OPERATING THE SAME
3D NAND 3D SEMICIRCULAR VERTICAL NAND STRING WITH SELF ALIGNED FLOATING GATE OR CHARGE TRAP CELL MEMORY CELLS AND METHODS OF FABRICATING AND OPERATING THE SAME
The memory device includes a plurality of memory cells arranged in a string substantially perpendicular to a major surface of the substrate 10 at a plurality of device levels, at least one first select gate located between a main surface of the substrate and a plurality of memory cells, A semiconductor channel (601) having an electrode, at least one second select gate electrode located over a plurality of memory cells, a portion extending vertically along a direction perpendicular to the main surface, a first A memory film 54, and a second memory film 54 in contact with the second side of the semiconductor channel. The second memory film is electrically isolated from the first memory film and positioned at the same level as the first memory film.
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