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Instruction and logic for the detection of a numerical accumulation error

机译:检测数字累积误差的指令和逻辑

摘要

A processor includes circuitry for decoding at least one instruction and execution unit. The decoded statement can calculate a floating point result. The execution unit includes circuitry to execute the instruction, determine the floating point result, calculate the amount of lost accuracy in a mantissa of the floating point result, compare the amount of lost accuracy with a precision limit of the numerical accumulation error based determine on the comparison if a numerical accumulation error has occurred and write a value to a flag. The amount of lost precision corresponds to several lost bits in the mantissa of the floating point result. The value written to the flag may be based on the determination that the numerical accumulation error has occurred. The flag may serve to indicate that the numerical accumulation error has occurred.
机译:一种处理器,包括用于解码至少一个指令和执行单元的电路。解码后的语句可以计算浮点结果。执行单元包括用于执行指令,确定浮点结果,计算浮点结果的尾数的精度损失量,将精度损失量与数值累加误差的精度极限进行比较的电路,基于比较是否发生了数值累加错误,并将值写入标志。精度损失的数量对应于浮点结果的尾数中的几个丢失的位。写入标志的值可以基于已经发生数值累积误差的确定。该标记可以用来指示已经发生了数值累积误差。

著录项

  • 公开/公告号DE112017004911T5

    专利类型

  • 公开/公告日2019-06-13

    原文格式PDF

  • 申请/专利权人 INTEL CORPORATION;

    申请/专利号DE112017004911T5

  • 发明设计人 ILAN PARDO;OREN BEN-KIKI;

    申请日2017-08-30

  • 分类号G06F11/07;G06F7/483;

  • 国家 DE

  • 入库时间 2022-08-21 11:44:58

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