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Apparatus and method for performing transformations of packed complex data with real and imaginary components

机译:用于执行具有实部和虚部分量的打包的复杂数据的转换的设备和方法

摘要

An apparatus and method for performing transformation on complex data. For example, one embodiment of a processor includes: a decoder for decoding a first instruction to generate a decoded instruction; a first source register for storing a first plurality of packed real and imaginary data elements; a second source register for storing a second plurality of packed real and imaginary data elements; a third source register for storing a third plurality of packed real and imaginary data elements; an execution circuit for executing the decoded instruction, the execution circuit comprising: a multiplier circuit for selecting real and imaginary data elements in the first and second source registers to multiply based on an immediate element of the first instruction, the multiplier circuit receiving first packed data items from the first source register multiplied by second packed data elements from the second source register according to the immediate element to produce a plurality of real and imaginary products, an adder circuit for selecting real and imaginary data elements in the third source register based on the immediate element, the adder circuit having selected true and adding and subtracting imaginary values from the real and imaginary products to produce first real and imaginary results; a scaling, rounding and / or saturating circuit for scaling, rounding and / or saturating the first true and imaginary results to produce real and imaginary end data elements; and a destination register for storing the real and imaginary end data items in predetermined data item positions.
机译:一种对复杂数据进行变换的装置和方法。例如,处理器的一个实施例包括:解码器,用于解码第一指令以生成解码指令;以及第一源寄存器,用于存储第一多个打包的实数和虚数数据元素;第二源寄存器,用于存储第二多个打包的实数和虚数数据元素;第三源寄存器,用于存储第三组打包的实部和虚部数据元素;执行电路,用于执行解码后的指令,该执行电路包括:乘法器电路,用于选择第一和第二源寄存器中的实数和虚数数据元素以基于第一指令的立即数进行乘法,该乘法器电路接收第一打包数据来自第一源寄存器的项乘以根据立即数元素来自第二源寄存器的第二打包数据元素,以产生多个实数和虚数乘积;加法器电路,用于基于第三元素在第三源寄存器中选择实数和虚数数据元素立即单元,加法器电路选择了真,并从实和虚积中减去虚值以产生第一实和虚结果;缩放,四舍五入和/或饱和电路,用于缩放,四舍五入和/或饱和第一和第二结果,以产生实数和虚数最终数据元素;目的地寄存器,用于在预定的数据项位置存储实数和虚数结束数据项。

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