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FP16-S7E8 MIXED-PRECISION FOR DEEP LEARNING AND OTHER ALGORITHMS
FP16-S7E8 MIXED-PRECISION FOR DEEP LEARNING AND OTHER ALGORITHMS
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机译:FP16-S7E8用于深度学习和其他算法的混合精度
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摘要
Disclosed embodiments relate to mixed-precision vector multiply-accumulate (MPVMAC) In one example, a processor includes fetch circuitry to fetch a compress instruction having fields to specify locations of a source vector having N single-precision formatted elements, and a compressed vector having N neural half-precision (NHP) formatted elements, decode circuitry to decode the fetched compress instruction, execution circuitry to respond to the decoded compress instruction by: converting each element of the source vector into the NHP format and writing each converted element to a corresponding compressed vector element, wherein the processor is further to fetch, decode, and execute a MPVMAC instruction to multiply corresponding NHP-formatted elements using a 16-bit multiplier, and accumulate each of the products with previous contents of a corresponding destination using a 32-bit accumulator.
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