RC OSCILLATOR WATCHDOG CIRCUIT

摘要

An RC oscillator (fig. 3: 6) generates a periodic trigger signal (fig. 3, 4: Sc), and a clock generator (fig. 3: 22) generates clock edges in response (fig. 3: CLK2). A stuck-at-fault detection circuit (fig. 3, 4: 100) detects a stuck-at-logic state (fig. 3, 4, 5: SC fixe at 1) of the periodic trigger signal and causes the RC oscillator to reset (fig. 3: 100 out, fig. 4: ClkMon_Stop_B ) and causes a change in logic state of the periodic trigger signal (fig. 3, 4, 5: Sc at 0).;The RC oscillator (fig. 3: 6) includes first and second comparison circuits (fig. 3: 80, 81), a logic circuit (fig. 3: 84) receiving output from the first and second comparison circuits and generating the periodic trigger signal (Sc), and a clock generation circuit (fig. 3, 4: 100) generating a clock signal therefrom (fig. 3: CLK2).;The stuck-at-fault detection circuit (fig. 3, 4: 100) includes a capacitive node (Cap Node), charge circuitry (102, M1, M2) charging the capacitive node based upon the periodic trigger signal (Sc), discharge circuitry (102, M4, M5) discharging the capacitive node based upon the periodic trigger signal (Sc), and triggering circuitry (104, 106, 108, 110, 112) asserting a reset signal (ClkMon_Stop_B) to cause the RC oscillator to reset when the charge on the capacitive node (Cap_Node) indicates a stuck-at-logic state of the periodic trigger signal (Sc).