Circuit, system, and method implemented by a processor with a plurality of reconfigurable units reconfigurable to compute a combined result

摘要

A circuit includes a resettable unit that can be reset to calculate a combination result. A first intermediate result of a first one of the resettable units is exchanged with a second intermediate result of a second one of the resettable units. The first resettable unit utilizes the second intermediate result to calculate a first portion of the combined result. A second one of the resettable units utilizes the first intermediate result to calculate a second portion of the combined result. [Selection] Figure 2