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Ternary signal generating device, ternary signal generating method, pulse pattern generating device, and pulse pattern generating method

机译:三元信号产生装置,三元信号产生方法,脉冲图案产生装置和脉冲图案产生方法

摘要

To generate a three-value signal of LFPS signal set forth in USB 3.0/3.1 standard.SOLUTION: A three-value signal generator 2 comprises: a logic circuit unit 11 for outputting the logical product signal of a most significant bit and a least significant bit, the logical sum signal of a most significant bit and a least significant bit, and a most significant bit; a variable amplification unit 12 including a variable amplifier 12a for amplifying the logical product signal, a variable amplifier 12b for amplifying the most significant bit, and a variable amplifier 12c for amplifying the logical sum signal; an addition unit 13 for adding the output of the variable amplifier 12a and the output of the variable amplifier 12b together, and outputting a second addition signal consisting of a first addition signal resulting from this addition plus the output of the variable amplifier 12c; and a control unit 14 for defining that when the three-value signal is off, the most significant bit is at a low level and the least significant bit is at a high level, and controlling the amplitude levels of the variable amplifiers 12a, 12b, 12c independently of each other so that the amplitude levels of the first and second addition signals are equal.SELECTED DRAWING: Figure 1
机译:为了产生USB 3.0 / 3.1标准中提出的LFPS信号的三值信号。解决方案:三值信号发生器2包括:逻辑电路单元11,用于输出最高有效位和最低有效位的逻辑积信号。位,最高有效位,最低有效位和最高有效位的逻辑和信号;可变放大单元12包括:可变放大器12a,用于放大逻辑乘积信号;可变放大器12b,用于放大最高有效位;以及可变放大器12c,用于放大逻辑和信号;加法单元13,用于将可变放大器12a的输出与可变放大器12b的输出相加,并输出第二加法信号,该第二加法信号包括由该加法运算得到的第一加法信号加上可变放大器12c的输出;控制单元14,用于定义当三值信号关闭时,最高有效位为低电平,最低有效位为高电平,并控制可变放大器12a,12b的幅度电平,图12c彼此独立,因此第一和第二加法信号的幅度电平相等。

著录项

  • 公开/公告号JP6651568B2

    专利类型

  • 公开/公告日2020-02-19

    原文格式PDF

  • 申请/专利权人 アンリツ株式会社;

    申请/专利号JP20180073156

  • 发明设计人 南 昂孝;柴田 和也;

    申请日2018-04-05

  • 分类号H04L25/49;

  • 国家 JP

  • 入库时间 2022-08-21 11:32:52

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