首页> 外国专利> Calibration circuit including common node shared by pull-up calibration path and pull-down calibration path, and semiconductor memory device including the same

Calibration circuit including common node shared by pull-up calibration path and pull-down calibration path, and semiconductor memory device including the same

机译:包括上拉校准路径和下拉校准路径共享的公共节点的校准电路以及包括该校准电路的半导体存储器件

摘要

A calibration circuit includes first and second pull-up units each receiving a pull-up code and connected between a pad connected with an external resistor and a first power supply voltage, a pull-down unit connected between the pad and a second power supply voltage and receiving a pull-down code, a comparator comparing a first voltage with a reference voltage and then compare a second voltage with the reference voltage, a first digital filter adjusting the pull-up code based on a first comparison result of the first voltage with the reference voltage, and a second digital filter adjusting the pull-down code based on a second comparison result of the second voltage with the reference voltage.
机译:校准电路包括第一和第二上拉单元,每个上拉单元接收上拉码并且连接在与外部电阻器连接的焊盘和第一电源电压之间,连接在该焊盘和第二电源电压之间的下拉单元接收到下拉代码的比较器将第一电压与参考电压进行比较,然后将第二电压与参考电压进行比较,第一数字滤波器基于第一电压的第一比较结果来调整上拉代码。第二数字滤波器基于第二电压与参考电压的第二比较结果来调节下拉代码。

著录项

  • 公开/公告号US10748585B2

    专利类型

  • 公开/公告日2020-08-18

    原文格式PDF

  • 申请/专利权人 SAMSUNG ELECTRONICS CO. LTD.;

    申请/专利号US201916353429

  • 发明设计人 HUN-DAE CHOI;

    申请日2019-03-14

  • 分类号G11C7/10;G11C11/408;H03K17/687;

  • 国家 US

  • 入库时间 2022-08-21 11:31:07

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