Testing method for testing wafer level chip scale packages
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机译:用于测试晶片级芯片级封装的测试方法
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摘要
A testing method for testing wafer level chip scale packages formed on a wafer including a wafer substrate and spaced-apart contact electrodes disposed on the wafer substrate, includes: providing a test device including a probe card formed with a plurality of parallel probe holes having a uniform cross-sectional dimension, and a plurality of probes respectively received in the probe holes and extending respectively in the probe holes along axes of the probe holes; and electrically connecting the contact electrodes to the probes. A distance between the axes of two adjacent ones of the probe holes is equal to a smallest spacing between two adjacent ones of the contact electrodes and is not greater than 0.5 mm.
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