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System and methodology that facilitates error management within a shared non-volatile memory architecture

机译:有助于在共享的非易失性存储器架构中进行错误管理的系统和方法

摘要

Various aspects directed towards facilitating error management within a shared non-volatile memory (NVM) architecture are disclosed. Data programmed into a plurality NVM cells is encoded prior to programming, and a range of programmability associated with each of the plurality of NVM cells is determined when the plurality of NVM cells are programmed A first error management scheme is then applied to NVM cells identified as limited-range programmable cells, and a second error management scheme is applied to NVM cells identified as full-range programmable cells, such that the second error management scheme is different than the first error management scheme.
机译:公开了旨在促进共享非易失性存储器(NVM)架构内的错误管理的各个方面。被编程到多个NVM单元中的数据在编程之前被编码,并且当对多个NVM单元进行编程时,确定与多个NVM单元中的每一个相关联的可编程性的范围。然后,将第一错误管理方案应用于被标识为NVM的NVM单元。有限范围的可编程单元,并且将第二错误管理方案应用于标识为全范围可编程单元的NVM单元,使得第二错误管理方案不同于第一错误管理方案。

著录项

  • 公开/公告号US10514867B2

    专利类型

  • 公开/公告日2019-12-24

    原文格式PDF

  • 申请/专利权人 WESTERN DIGITAL TECHNOLOGIES INC.;

    申请/专利号US201615396238

  • 发明设计人 LUIZ M. FRANCA-NETO;

    申请日2016-12-30

  • 分类号G06F3/06;G11C15/04;G06F11/10;G11C11/406;G11C16/34;

  • 国家 US

  • 入库时间 2022-08-21 11:28:21

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