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Testing mechanism for a proximity fail probability of defects across integrated chips
Testing mechanism for a proximity fail probability of defects across integrated chips
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机译:跨集成芯片缺陷的接近失效概率的测试机制
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摘要
According to an embodiment, a testing mechanism determines a status of circuits within a chip by analyzing fail signatures on a by-level basis to identify a high probability defect area within the chip. The testing mechanism further determines a whether functionally needed circuitry of the chip intersects with the high probability defect area within the chip and determines the status of the circuits in response to the determining of whether the functionally needed circuitry intersects with the high probability defect area.
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