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Method, design program, and design apparatus of a high level synthesis process of a circuit

机译:电路的高级综合过程的方法,设计程序和设计设备

摘要

A design method including a high level synthesis process that has (1) generating a hardware description of a circuit and high level synthesis report information from a source code based on a high level synthesis constraint, the hardware description describing a circuit including a plurality of stages and inter-stage registers; (2) determining a bypass stage selection pattern based on bypass constraint information including a constraint condition related to a bypass of the inter-stage register and the high level synthesis report information, the bypass stage selection pattern including a plurality of patterns each pattern having a combination of stages of inter-stage registers for which bypass setting is performed among stages of a bypass setting-capable inter-stage registers; and (3) generating bypass report information based on the bypass stage selection pattern, the bypass report information including combination information of the inter-stage registers for which the bypass is performed setting corresponding to a predetermined priority condition.
机译:一种包括高级综合过程的设计方法,该方法具有(1)基于高级综合约束从源代码生成电路的硬件描述和高级综合报告信息,该硬件描述描述了包括多个阶段的电路和级间寄存器; (2)基于包括与级间寄存器的旁路相关的约束条件的旁路约束信息和高级综合报告信息,确定旁路级选择模式,该旁路级选择模式包括多个模式,每个模式具有具有旁路设置能力的级间寄存器的各级之间进行旁路设置的级间寄存器的级的组合; (3)基于旁路级选择模式生成旁路报告信息,该旁路报告信息包括与预定优先级条件相对应地设置的对其进行旁路的级间寄存器的组合信息。

著录项

  • 公开/公告号US10606972B2

    专利类型

  • 公开/公告日2020-03-31

    原文格式PDF

  • 申请/专利权人 SOCIONEXT INC.;

    申请/专利号US201815968327

  • 发明设计人 ATSUSHI YASUNAKA;

    申请日2018-05-01

  • 分类号G06F17/50;

  • 国家 US

  • 入库时间 2022-08-21 11:28:07

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