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Staggered transmissions on a multi-drop half-duplex bus

机译:多点半双工总线上的交错传输

摘要

Systems, methods, and apparatus for optimizing bus latency associated with a serial bus using staggered bidirectional transmission within a transaction or datagram are described. A method performed at a device coupled to a serial bus includes initiating a transaction between the first device and a second device to exchange a datagram with the second device in a first direction over the serial bus, and exchanging one or more bytes of data with the second device in a second direction over the serial bus before the datagram has been completely transmitted. The first device and the second device alternate as transmitters on the serial bus such that direction of data transmission is staggered on the serial bus. The serial bus may be operated in accordance with an I3C, RFFE, SPMI, or other protocol.
机译:描述了用于使用事务或数据报内的交错双向传输来优化与串行总线相关联的总线等待时间的系统,方法和装置。在耦合到串行总线的设备上执行的方法包括:启动第一设备和第二设备之间的事务,以通过串行总线在第一方向上与第二设备交换数据报,以及与第二设备交换一个或多个字节的数据。在数据报已完全传输之前,第二个设备在第二方向通过串行总线。第一设备和第二设备交替作为串行总线上的发送器,使得数据传输的方向在串行总线上错开。可以根据I3C,RFFE,SPMI或其他协议来操作串行总线。

著录项

  • 公开/公告号US10579549B2

    专利类型

  • 公开/公告日2020-03-03

    原文格式PDF

  • 申请/专利权人 QUALCOMM INCORPORATED;

    申请/专利号US201816162583

  • 申请日2018-10-17

  • 分类号G06F13/36;G06F13/16;G06F3/06;H04B7/26;H04L25/497;H04L12/40;G06F13/42;

  • 国家 US

  • 入库时间 2022-08-21 11:26:57

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