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ELECTRICAL IMPEDANCE TOMOGRAPHY WITH FDM-BASED DATA COMPRESSION

机译:基于FDM的数据压缩的电抗断层成像

摘要

An electrical impedance tomography system with frequency division multiplexing based data compression comprising electrodes, a connecting line, an electrical impedance tomography chip, a universal serial bus and a computer. The present invention realizes the proposed electrical impedance tomography system by innovative application of frequency division multiplexing technology, and has the advantages of low power consumption and improved hardware overheads. The architecture of the 13-channel electrical impedance tomography chip introduced in the embodiment of the present invention, which applies the frequency division multiplexing based data compression technology, has taped out using CMOS 0.13 micrometer process; the power consumption per channel turns out to be 118 microwatts and the area is 0.87 square millimeters, verifying the effectiveness of the present invention. The present invention can also be migrated to other applications of electrical impedance tomography.
机译:一种具有基于频分复用的数据压缩的电阻抗层析成像系统,包括电极,连接线,电阻抗层析成像芯片,通用串行总线和计算机。本发明通过频分复用技术的创新应用,实现了所提出的电阻抗层析成像系统,具有功耗低,硬件开销提高的优点。本发明实施例中引入的13通道电阻抗层析成像芯片的架构,采用了基于频分复用的数据压缩技术,已经采用CMOS 0.13微米工艺进行了流片;每通道的功率消耗为118微瓦,面积为0.87平方毫米,证明了本发明的有效性。本发明还可以迁移到电阻抗层析成像的其他应用。

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